Circuit timing can impact the power, performance, noise, and area of a circuit. Timing can be adjusted by many alternative circuit design styles, which can provide benefits over industry standard clocked design methods and technology. Timing can also be a primary impediment to the commercialization and adoption for these alternative circuits. Asynchronous circuit design is an example of a circuit family that uses alternative timing. At a circuit and architectural level, asynchronous design uses a continuous timing model, whereas clocked design uses a discrete model of time based on clock cycles.
Two general methods for signal sequencing have emerged in the design community: Clocked and asynchronous. Clocked design is founded upon frequency based protocols that define discrete clock periods. Clocked methods contain combinational logic (CL) between latches or flip-flops creating pipeline stages that are controlled by a common frequency. All other methods besides clocked methods can be considered “asynchronous”, including but not limited to methods that employ handshake protocols, self-resetting domino circuits, and embedded sequential elements, such as static random-access memory (SRAM), dynamic random-access memory (DRAM), read-only memory (ROM), or programmable logic arrays (PLA). Asynchronous elements can contain state-holding circuits, such as sequential controllers, domino gates, or memory elements. The arrival of inputs to an asynchronous circuit may not be based on a global clock frequency. Delays through an asynchronous circuit can vary based on function, application, manufacturing variations, and operating parameters, such as temperature and voltage fluctuations.
Reference will now be made to the exemplary embodiments illustrated, and specific language will be used herein to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended.